This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-107252, filed Apr. 5, 2001, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor power device and, more particularly to, an insulated gate bipolar transistor (IGBT), which is applicable to a power conversion inverter (power converter).
2. Description of the Related Art
A demand for a smaller size and a higher performance of a power device in the field of recent power electronics has brought attention toward improvements in performance such as a higher breakdown voltage, a larger current handling capability, a lower loss, a higher disruptive discharge voltage, and a higher operating speed. As such, a power IGBT is now used as a semiconductor power device that has a breakdown voltage of not less than 300V and can flow a higher current therethrough.
The power IGBT""s include two well known structures: a planar type IGBT that has an insulating gate, for example, a flat MOS gate, and a trench type IGBT in which the MOS gate is buried in a trench. The trench type IGBT has the trench gate structure in which a number of trench IGBT cells in which the trench-side wall serves as a channel region are arrayed in parallel in a semiconductor substrate. Generally, the trench type IGBT is said to be more advantageous than the planar type IGBT because it can enjoy a lower channel resistance to thereby, for example, easily reduce the loss.
FIG. 1 is a schematic cross-sectional view for showing part of a conventional trench type IGBT. In the IGBT, a p type base layer 107 is formed in a surface region of a high-resistance nxe2x88x92 type base layer 101. A plurality of trenches 104 is formed in a surface region of the p type base layer 107 into the nxe2x88x92 type base layer 101. In each of these trenches 104, a trench gate electrode 106 is buried via a gate insulating film 105. In the surface region of the p type base layer 107 which sandwiched by these trenches 104, a high impurity-concentration n+ type emitter layer 108 is formed adjacent the side surface of the trench 104. It should be noted that a gate electrode 106 of each trench is drawn out to, for example, a wide gate-electrode contacting pad.
An emitter electrode 109 is provided on the surfaces of the n+ type emitter layer 108 and the p type base layer 107. The emitter electrode 109 short-circuits the n+ type emitter layer 108 and the p type base layer 107 to each other. Furthermore, an inter-layer insulating film 111 is provided on the trench gate electrode 106. The inter-layer insulating film 111 is interposed between the trench gate electrode 106 and the emitter electrode 109 to thereby prevent them from being short-circuited to each other.
The nxe2x88x92 type base layer 101, p type base layer 107, n+ type emitter layer 108, gate insulating film 105, and trench gate electrode 106 constitute a MOSFET. Electrons are injected from the n+ type emitter layer 108 into the nxe2x88x92 type base layer 101 through a channel region of the MOSFET. The channel region of the MOSFET is formed at such a surface region of the p type base layer 107 as to be in contact with the trench 104.
A high impurity-concentration p+ type collector layer 103 is formed in the other surface region of the nxe2x88x92 type base layer 101 via an n+ type buffer layer 102. A collector electrode 110 is provided on the p+ type collector layer 103.
It should be noted that it is not necessary to form the above-mentioned n+ type buffer layer 102 if a desired breakdown voltage can be obtained otherwise. Furthermore, in the figure, E indicates an emitter electrode, G indicates a gate electrode, and C indicates a collector electrode.
FIG. 2 shows one example of a distribution of the impurity concentration on a cross section taken along line 2xe2x80x942 of FIG. 1. As shown in FIG. 2, an n type impurity concentration is constant in the thickness direction of the nxe2x88x92 type base layer 101.
The IGBT having the above-mentioned structure, however, has such a problem that with a decreasing turn-OFF loss, ON-state voltage drop increases extremely in the steady state and, conversely, with the decreasing ON-state voltage drop, the turn-OFF loss increases extremely.
To solve this problem in order to obtain minimum turn-OFF loss and ON-state voltage drop, there are two methods available. (1) conducting control so as to shorten the life time (the time required for a minority carrier to be recombined) by application of an electron beam. (2) using a thin transparent collector layer.
When any of these methods is used, particularly such a punch-through type IGBT having the nxe2x88x92 type base layer 101 and the n+ type buffer layer 102, the thickness of the nxe2x88x92 type base layer 101 must be sufficient to obtain a desired breakdown voltage in order to reduce the turn-OFF loss and the ON-state voltage drop in the steady state as much as possible. The thickness of the nxe2x88x92 type base layer 101 is generally selected according to a relationship of about 10 xcexcm/100V, for example.
Using the former method of life time control, a high concentration n+ buffer layer is formed by epitaxial growth in a high concentration p+ type substrate, in which is in turn formed a relatively high-resistance nxe2x88x92 type base layer by epitaxial growth to obtain an nxe2x88x92/n+/p+ type three-layer construction wafer in order to form thereon an IGBT having the above-mentioned structure.
By using such a life time control method, it is possible to obtain a punch-through type IGBT having a sufficiently low turn-OFF loss. However, the n+ type buffer layer 102 and the nxe2x88x92 type base layer 101 are thus formed sequentially in the p type substrate by epitaxial growth, meaning that this method increases the manufacture costs of the wafer.
By the latter method of using a thin transparent collector layer, a wafer manufactured by the floating zone (FZ) method or the Chokralski Zone (CZ) method is ground to a minimum thickness required to obtain a desired breakdown voltage, p type impurities such as boron ions are injected into a surface of the wafer to form a transparent p type collector layer with a thickness of about 1 xcexcm, thereby form a MOS structure in the other surface of the wafer.
The method of using such a thin transparent collector layer, however, has a problem that in order to decrease the ON-state voltage drop and the turn-OFF loss as much as possible, the wafer must be very thin and so very difficult to manufacture.
According to one example of a method for manufacturing a trench type IGBT having a breakdown voltage of 1200V, for example, the p type base layer 107, the n+ type emitter layer 108, the trench 104, the gate insulating film 105, the trench gate electrode 106, and the emitter electrode 109 are formed in a semiconductor substrate, respectively, then the semiconductor substrate is ground to a thickness of 120 xcexcm, n type and p type impurity ions are implanted to form the n+ type buffer layer 102 and the p+ type collector layer 103, respectively. In this process, to activate these n type and p type impurity ions, so that they may serve as a donor and an acceptor respectively, it is necessary to conduct heat treatment at 800xc2x0 C. or higher. This heat treatment, however, brings about a problem that, for example, a surface-patterned emitter electrode 109 may be melted, thus destroying the electrode pattern. Moreover, as the wafer is ground thin, as mentioned above, it warps greatly, thus making it extremely difficult to pattern the emitter electrode 109 before heat treatment.
Further, the above-mentioned methods both have a problem that the wafer may be damaged due to a change in thermal stress during the heat treatment. In addition, according to a method of activating impurity ions by, for example, annealing them by applying an energy light such as a pulse laser in place of conducting heat treatment by use of a diffusion furnace, the impurity ions can be activated only down to 1 xcexcm or so from the wafer surface. It is therefore extremely difficult to form the n+ type buffer layer 102 which needs to be deep as much as 1 xcexcm or more from the wafer surface, by activating and diffusing n type impurity ions. That is, a punch-through type IGBT using the above-mentioned thin semiconductor substrate suffers from a problem in that it is extremely difficult to manufacture.
It should be noted that in such a trench type IGBT having a structure shown in FIG. 1, if a spacing (cell pitch) between the trench electrodes 106 is relatively large and a contact opening width is also large as compared to a processing accuracy, the n+ type emitter layer 108 and the p type base layer 107 are short-circuited to each other via the emitter electrode 109 throughout the surface in a direction parallel to the trench 104.
As the cell pitch decreases, on the other hand, the contact opening becomes small in width, thus making it difficult to short-circuit the n+ type emitter layer 108 and the p type base layer 107 to each other via the emitter electrode 109 throughout the surface in the direction parallel to the trench 104. To solve this problem, a suggestion is made to form the n+ type emitter layer 108 of the trench type IGBT so that it may have a ladder-shaped plane pattern, that: is, so that the p type base layer 107 may be exposed in a square as much as possible.
Another suggestion is made to form the n+ type emitter layer 108 so that it may have an overall mesh-shaped or offset mesh-shaped plane pattern, that is, so that a stripe-shaped exposed portion of the n+ emitter layer 108 and that of the n type base layer 107 may alternate with each other along the trench 104.
A further suggestion is made to form an emitter contact trench in the p type base layer 107 between the mutually opposing n+ type emitter layers 108 so that the emitter electrode 109 may be formed in this trench in such a manner as to come in contact with the side surface of the n+ type emitter layer 108 and the p type base layer 107.
A trench type IGBT having any one of the above-mentioned various structures also has a problem similar to that of a trench gate type IGBT having the structure shown in FIG. 1. Furthermore, the planar type IGBT has almost the same problem as the trench type IGBT.
Furthermore, such the planar type IGBT is known, as disclosed in, for example, Jpn. Pat. Appln. KOKAI No. 11-40808. This disclosed planar type IGBT has such an inclination-distributed region in which the impurity concentration is continuously changed that is formed at an n+ type buffer layer of n type drift layers, in order to improve the OFF state characteristics without increasing the overall thickness and the turn-ON resistance or the leakage current.
This planar type IGBT, however, is formed of an nxe2x88x92/n+/p+ three-layer structure wafer obtained by forming a high-concentration n+ type buffer layer by epitaxial growth on a p+ type high-concentration substrate and then forming thereon a relatively high-resistance nxe2x88x92 type base layer also by epitaxial growth.
By conducting life time control on the thus obtained planar type IGBT, the turn-OFF loss can be reduced. However, the n+ type buffer layer and the nxe2x88x92 type base layer are sequentially formed on the p type substrate by epitaxial growth, which raises the problem of increased wafer manufacturing costs. Moreover, the p type collector layer has a considerable thickness, meaning that the overall thickness cannot be reduced.
As mentioned above, the conventional punch-through type IGBT has a problem of a high manufacture cost of an employed semiconductor substrate according to the method of conducting life time control in order to obtain a minimum required turn-OFF loss and the ON-state voltage drop and also has a problem of an extremely thin semiconductor substrate and hence a difficulty in manufacture thereof by the method of using a thin transparent collector layer.
According to one aspect of the present invention, there is provided a semiconductor power device comprises, a first base layer containing an impurity of a first conductivity type so as to have a concentration gradient which continuously changes in a thickness direction thereof, a second base layer containing an impurity of a second conductivity type formed in one surface region of the first base layer, a trench having such a depth as to reach from a surface of the second base layer through the second base layer to the first base layer, an emitter layer containing an impurity of the first conductivity type formed in the surface region of the second base layer in such a manner so as to be in contact with the trench, a gate electrode formed in the trench, a collector layer formed in the other surface of the first base layer, the collector layer contains an impurity of the second conductivity type and has a thickness of 1 xcexcm or less, a first main electrode continuously formed on the emitter layer and the second base layer, and a second main electrode formed on the collector layer.
Furthermore, according to another aspect of the present invention, there is provided a method for manufacturing a semiconductor power device comprises, introducing an impurity of a first conductivity type into a semiconductor substrate from one surface to form a first base layer, the first base layer having a concentration gradient which continuously changes in a thickness direction thereof, introducing an impurity of a second conductivity type into the first base layer to form a second base layer, introducing an impurity of the first conductivity type into the second base layer to form an emitter layer, forming a trench in the emitter layer, the trench having a depth that reaches through the second base layer to the first base layer, forming a gate electrode in the trench, forming a conductive layer on the resultant structure, then patterning the conductive layer to form a first main electrode continuously on the second base layer and the emitter layer, removing the first base layer from the other surface to provide a desired thickness of the first base layer, introducing an impurity of the second conductivity type into the other surface of the first base layer to form a collector layer, and forming a second main electrode on an exposed surface of the collector layer.